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Intel® Embedded Graphics Drivers FAQ

Display resolutions

1.  What is the minimum standard active resolution supported by the integrated low-voltage differential signaling (LVDS) display controller on the Intel® System Controller Hub US15W chipset and Intel® Embedded Graphics Drivers?


The software does not impose any limits; however, developers need to be sure the chipset’s design specs are not violated. The minimum pixel clock frequency supported and validated on the Intel® System Controller Hub US15W chipset is 20 MHz. The minimum standard active resolution is therefore 640x480 @ 50 Hz vertical refresh, which equates to ~20 MHz pixel clock. It may be possible to pad the horizontal and vertical blanking and adjust the refresh rate higher to get a lower resolution at the minimum 20 MHz pixel clock, but that is something that needs to be explored with the LCD panel manufacturer.


2.  What is the minimum and maximum custom active resolution supported by the integrated LVDS display controller on the Intel® System Controller Hub (Intel® SCH) US15W chipset and the Configuration EDitor (CED)?


Theoretically, any timing mode that yields a pixel clock frequency between 20 MHz and 112 MHz (maximum allowable pixel clock frequency for the Intel SCH US15W chipset internal LVDS controller) can be supported by Intel® Embedded Graphics Drivers and the Intel SCH US15W chipset. To determine if a particular timing mode can be supported, use the following formula to determine the pixel clock frequency, and then determine if it is between 20 MHz and 112 MHz:


Using 720 x 480 @ 60 Hz as an example:


pixel clock frequency = HTOTAL * VTOTAL * Vertical Refresh Rate / 1000000


HACTIVE = 720 pixels / line
HBLANK_BACK PORCH = 10 pixels / line
HBLANK_FRONT PORCH = 128 pixels / line
HTOTAL = HACTIVE + HBLANK_BACK PORCH + HBLANK_FRONT PORCH
HTOTAL = 720 + 10 + 128 = 858 pixels / line


VACTIVE = 480 lines / frame
VBLANK_BACK PORCH = 19 lines / frame
VBLANK_FRONT PORCH = 26 lines / frame
VTOTAL = VACTIVE + VBLANK_BACK PORCH + VBLANK_FRONT PORCH
VTOTAL = 480 + 19 + 26 = 525 lines / frame


pixel clock frequency = HTOTAL * VTOTAL * Vertical Refresh Rate / 1000000
pixel clock frequency = 858 pixels / line * 525 lines / frame * 60 Hz / 1000000
pixel clock frequency = 27.027 MHz


pixel clock frequency > 20 MHz so 720 x 480 @ 60 Hz can be supported by Intel® Embedded Graphics Drivers via the CED application.


3.  What are the minimum and maximum standard active resolutions supported by the integrated serial digital video out (SDVO) display controller on the Intel® System Controller Hub US15W chipset?


The minimum pixel clock frequency supported by the Intel® SCH US15W chipset SDVO interface is 20 MHz. The minimum standard active resolution is therefore 640x480 @ 50 Hz vertical refresh, which equates to ~20 MHz.


The maximum pixel clock frequency supported by the Intel SCH US15W chipset SDVO interface is 160 MHz. The maximum standard active resolution is therefore 1920x1080 @ 60 Hz vertical refresh, which equates to ~148.5 MHz pixel clock. Common high resolutions, such as 1600x1200 and 1280x1024, are also supported since they possess pixel clock rates less than 160 MHz.


Any timing mode that yields a pixel clock frequency that is between 20 MHz and 160 MHz can be supported by Intel® Embedded Graphics Drivers and the Intel SCH US15W chipset via SDVO. Check your chosen SDVO device vendor’s data sheet for limitations of the display output. Most Video Graphics Array (VGA) and television encoders cannot support analog cathode ray tube (CRT), high-definition television (HDTV), and standard-definition television (SDTV) outputs whose pixel clock rates exceed 80 MHz.


For additional details on the graphics capabilities, please refer to Intel® System Controller Hub US15W chipset.

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