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PCI 16-Bit Read Implementations for IXP42X Product Line: App Note

PCI 16-Bit Read Implementations for IXP42X Product Line: App Note

This document describes the PCI 16-bit memory read implementation reference design of the IXP42X product line and IXC1100 Control Plane Processor. The IXP42X product line and IXC1100 control plane processors’ PCI controller drives all byte enables low (asserted) during a memory cycle read of non-prefetch memory. However, I/O reads and memory-cycle writes do drive individual byte enables.

If an external PCI device has non-prefetch memory and requires either a 16-bit or 8-bit read, there is a possibility that the device will not respond correctly to the IXP42X product line and IXC1100 control plane processors’ memory reads. This is because the processors always perform a 32-bit read to the non-prefetch memory region specified in register PCI_NP_AD.

Read the full PCI 16-Bit Read Implementations for IXP42X Product Line Application Note.

PCI 16-Bit Read Implementations for IXP42X Product Line: App Note

This document describes the PCI 16-bit memory read implementation reference design of the IXP42X product line and IXC1100 Control Plane Processor. The IXP42X product line and IXC1100 control plane processors’ PCI controller drives all byte enables low (asserted) during a memory cycle read of non-prefetch memory. However, I/O reads and memory-cycle writes do drive individual byte enables.

If an external PCI device has non-prefetch memory and requires either a 16-bit or 8-bit read, there is a possibility that the device will not respond correctly to the IXP42X product line and IXC1100 control plane processors’ memory reads. This is because the processors always perform a 32-bit read to the non-prefetch memory region specified in register PCI_NP_AD.

Read the full PCI 16-Bit Read Implementations for IXP42X Product Line Application Note.

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