- 28 nm process
- Up to 52 million equivalent ASIC gates
- Up to 124 Mb of true dual port memory
- Up to 32 28 Gbps high speed transceivers
- Up to 32 16.3 Gbps high speed transceivers
Intel® eASIC™ devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs that provide lower unit-cost and lower power compared to FPGAs and faster time-to-market and lower non-recurring engineering cost compared to standard-cell ASICs. Intel eASIC devices provide fast time-to-deployment of logic, DSP or IO dominated custom devices. The current generation of products feature up to 52 million equivalent ASIC gates, 124 Mb of true dual port memory, and transceiver data rates of up to 28 Gbps.
Provides unit-cost and power reductions compared to FPGA by replacing SRAM configuration logic with patented single-via customization technology and disconnecting power from unused device structures.
Faster time to market and turnaround time than traditional ASICs due to simplified design flow, customization of only a few mask layers, and when feasible no PCB change from base FPGA designs.
The structured ASIC combines logic, memory, DSP, high speed memory interfaces, and high-speed transceivers (up to 28 Gbps) for high performance data plane or control plane applications.
A wealth of fully verified eASIC-ready IP cores from Intel and third party alliance partners.
Intel® eASIC™ device eTools offer a framework for design conversion and validation using a combination of internally developed and industry standard third party tools.
Intel® eASIC™ devices offer custom low power solutions for a broad range of data intensive and IO intensive applications in end markets such as 5G wireless, military, data center acceleration, compute, storage, machine learning inference, IoT, machine vision and video applications.