Article ID: 000073951 Content Type: Troubleshooting Last Reviewed: 03/21/2022

Why the clock frequency of the Cyclone® V HPS EMAC emac*_tx_clk exported to the FPGA fabric shown as 100Mhz in timing analysis?

Environment

  • Intel® Quartus® Prime Standard Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Starndard Edition Software version 20.1 and earlier, you can find GMII clock frequency is 100Mhz when enabling HPS EMAC and route it to FPGA in Cyclone® V SoC.

    Resolution

    To work around this problem in the Cyclone® V SoC HPS, you need to correct the period of emac*_tx_clk from 10ns to 8ns in cv_soc_rgmii_5csxfc6_hps_0_fpga_interfaces.sdc.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs