While Performing OpenCL import compile, user may experience following errors due to port mismatch
Error (18513): Child partition does not implement output signal which is required by parent partition
Error (18624): Partition contains output port that is ignored by its parent partition
In order to compile a kernel as an import, all the global memory ports as well as other added interfaces between static and PR region need to have an additional pipeline stage in kernel_system.qsys
This is automatically done by the OpenCL compiler when specifying addpipe=1 in board_spec.xml.
Here is an example:
<!-- Timestamp SRAM, 64-bit data -->
<global_mem name="TS_SRAM" max_bandwidth="1000" interleaved_bytes="8" config_addr="0x100"> <interface name="board" port="kernel_timestamp" type="slave" width="64" maxburst="1" address="0x200000000" size="0x000000800" latency="25" addpipe="1" />
</global_mem>