Article ID: 000074189 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the QDRII SRAM Controller report read_data_valid incorrectly when simultaneous reads and writes on a burst of four are performed?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

QDRII SRAM controller in Quartus® II and IP version 7.1 incorrectly reports read_data_valid in burst of 4 mode under following conditions:

  • Simultaneous reads and writes continuing 5 or more system clock cycles.
  • The first read is an odd address.

This issue has been fixed in Quartus II and IP version 7.2.

Related Products

This article applies to 1 products

Stratix® II FPGAs