Article ID: 000074196 Content Type: Troubleshooting Last Reviewed: 01/01/2015

PCI Express User Guide and Parameter Editor Allow Incorrect Application Clock Frequency for Stratix V GX Devices

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Gen1 × IP Compiler for PCI Express hard IP variations that target a Stratix V GX device support application clock frequency 125 MHz only. However, Table 4-1 in the PCI Express Compiler User Guide incorrectly indicates that this clock can also have frequency 62.5 MHz, and the PCI Express parameter editor allows the selection of 62.5 MHz or 125 MHz for this clock.

    All Gen1 × PCI Express compiler hard IP variations that target a Stratix V GX device.

    Resolution

    For these variations, select application clock frequency 125 MHz in the PCI Express compiler parameter editor.

    This issue is no longer relevant in version 11.0 of the IP Compiler for PCI Express and the IP Compiler for PCI Express Compiler User Guide. Stratix V device support is moved to the Stratix V Hard IP for PCI Express and the Stratix V Hard IP for PCI Express User Guide.

    In fact, the Stratix V Hard IP for PCI Express does support both the application frequency of 125 MHz and the application frequency of 62.5 MHz, and this fact is correctly documented in version 11.0 of the Stratix V Hard IP for PCI Express User Guide.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs