Article ID: 000074311 Content Type: Troubleshooting Last Reviewed: 03/16/2023

Are there any known issues with the "Use external receiver termination" option in the ALTGX Intel® FPGA IP?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, by default the "Use external receiver termination" option is turned off in the ALTGX Intel® FPGA IP in the Quartus® II software version 10.1 and previous versions, but if you turn this option on, internal termination will still be enabled.  You can verify this by looking at the Compilation Report - Fitter - Resource Section - Input Pins report.  The input termination value is shown in this report.

Resolution

If you wish to use external termination, you will need to add assignments to your receiver pins using the Assignment Editor following these steps:

  1. In the To column, add each receiver using the Node Finder that you will use external termination.
  2. In the Assignment Name column, select "Input Termination".
  3. In the Value column, select "Off".
  4. Compile your design.

This will disable the input termination for the selected receiver channels. 

Related Products

This article applies to 4 products

Arria® II GX FPGA
Cyclone® IV GX FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA