Article ID: 000074636 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the Arria II GX device DQS Phase Shift Error specification?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description The Arria® II GX device DQS phase shift error specification is shown in the table below:
Arria II GX DQS Phase Shift Error Specification

Number of DQS Delay Buffer

 
C4 speed grade
 
I3, I5, C5 speed grades
 
C6 speed grade

1

26ps

30ps

36ps

2

52ps

60ps

72ps

3

78ps

90ps

108ps

4

104ps

120ps

144ps

 

The phase shift error specification listed in the table is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a C4 speed grade is 78ps or /-39ps.

This specification will be included in the future release of the data sheet in the Arria II Device Handbook.

Related Products

This article applies to 1 products

Arria® II GX FPGA