Article ID: 000074688 Content Type: Error Messages Last Reviewed: 02/11/2023

Warning (332174): Ignored filter at outlvds_altera_lvds_core20_161_uedfafy.sdc(120)

Environment

  • LVDS SERDES Intel® FPGA IP
  • IOPLL Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see this warning message in the Quartus® Prime Software when implementing an external PLL with multiple Altera® LVDS SERDES instantiations which share the same lvds_clk and loaden, in Arria® 10 devices.

    Resolution

    To work around this warning, in the Altera IOPLL IP, create a pair of lvds_clk and loaden for each instantiation.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs