Article ID: 000074745 Content Type: Troubleshooting Last Reviewed: 12/01/2017

Is there any timing performance issue when the “ddio_l_reg” is implemented in the core logic when using the Altera Soft LVDS IP for MAX 10 devices?

Environment

  • Soft LVDS Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In MAX®10 devices, you may see the ddio_h_reg is in the I/O element and the ddio_l_reg is in core logic when using the Altera® Soft LVDS IP. This is expected implementation and will not affect timing performance.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs