Article ID: 000075589 Content Type: Troubleshooting Last Reviewed: 08/15/2023

Why does the P-Tile Debug Toolkit display lanes 8 – 15 registers in the P0 Configuration Space of a design configured in x8x8 mode ?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, lanes 8 – 15 registers are displayed in the P0 Configuration Space of a design configured in x8x8 mode. P0 Configuration Space should display lanes 0 – 7 registers only. Ignore the lane 8 – 15 registers.

    Resolution

    A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 21.2.
    Download and install Patch 0.23 from the appropriate link below.

    This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 21.3.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 DX FPGA
    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series