In the Intel® Arria® 10 Device Family Pin Connection Guidelines document version 2018.3.30 and earlier, the description of the nIO_PULLUP pin states "If you tie this pin to VCC, ensure all user I/O pins and dual-purpose I/O pins are at logic-0 before and during configuration". This is incorrect. The I/O pins can be driven to logic 0 or 1 after POR.
The Intel® Arria® 10 Device Family Pin Connection Guidelines document will be updated in release 2019.07.01 to indicate that the I/O pins and dual-purpse I/O pins can be driven to logic-0 or logic-1 after POR.