Article ID: 000076365 Content Type: Error Messages Last Reviewed: 09/11/2012

Critical Warning: <corename>_if0_p0_pin_map.tcl: Failed to find PLL clock for pins if0|p0|controller_phy_inst|memphy_top_inst|afi_half_clk_reg

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When compiling your DDR2 SDRAM or DDR3 SDRAM UniPHY design in the Quartus® II Software version 11.0 or 11.0SP1, you may experience the following critical warning:

    Critical Warning: <corename>_if0_p0_pin_map.tcl: Failed to find PLL clock for pins if0|p0|controller_phy_inst|memphy_top_inst|afi_half_clk_reg

    The critical warning does not occur on the first compile of the design but will occur on all subsequent compiles.

    The cause of the problem is RAPID_RECOMPILE_MODE set to ON which causes the afi_half_clk_reg to not be preserved in subsequent compiles.

    Resolution

    The workaround is to delete the db directory before the design is re-compiled or disable rapid recompile in your project.

    This issue will be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 5 products

    Stratix® III FPGAs
    Stratix® IV FPGAs
    Stratix® IV GX FPGA
    Stratix® IV GT FPGA
    Stratix® IV E FPGA