Article ID: 000076788 Content Type: Troubleshooting Last Reviewed: 07/27/2012

Internal Error: Sub-system: TIS_RC, File: /quartus/tsm/tis/tis_physical_timing_api.cpp, Line: 1334

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    During compilation of a design that targets an Arria V or Cyclone V device, compilation might fail with the error

    Internal Error: Sub-system: TIS_RC, File: /quartus/tsm/tis/tis_physical_timing_api.cpp, Line: 1334

    This error might occur if your design has high M10K block usage.

    Resolution

    If your design contains LogicLock regions, allow the Fitter to place memory elements outside of their assigned LogicLock region by performing the following steps:

    1. In the LogicLock Regions window, right-click a LogicLock region, and then click Properties.
    In the Members list of the Properties dialog box, select design elements.
    • Click Edit. The Edit Node dialog box opens.
    • Under Excluded element types, click Edit. The Excluded Element Types dialog box opens.
    • Under Excluded element types, turn on Memory.
    • If your design does not contain LogicLock regions, or if allowing the Fitter to place memory elements outside of their assigned LogicLock regions fails to resolve the error, add the following line to the quartus.ini file for your project:

      fitter_rams_disallow_packed_mode = on

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs