Article ID: 000077338 Content Type: Troubleshooting Last Reviewed: 04/18/2023

spl.c:239:8: error: 'CONFIG_SPL_SDRAM_ECC_PADDING' undeclared (first use in this function)

Environment

  • Intel® Quartus® Prime Standard Edition
  • Intel® SoC FPGA Embedded Development Suite Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® SoC FPGA Embedded Development Suite (SoC EDS), Preloader for Cyclone® V and Arria® V cannot compile when CONFIG_SPL_FPGA_LOAD macro is defined in software/spl_bsp/uboot-socfpga/include/configs/socfpga_common.h, and SDRAM ECC is enabled.

     

    Resolution

    To avoid this error, 'memset' function should be disabled with the #if/#endif macro below.

     

    software/spl_bsp/uboot-socfpga/arch/arm/cpu/armv7/socfpga/spl.c(245)             

         /* do memory padding as data in SDRAM */

    #if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN == 1)             

         filesize = file_fat_read(CONFIG_SPL_FPGA_FAT_NAME, NULL, 0);             

         if (filesize != -1) {                           

              memset((unsigned char *)((temp_sdram filesize)                                         

                              & ~(CONFIG_SPL_SDRAM_ECC_PADDING - 1)),

                              0, CONFIG_SPL_SDRAM_ECC_PADDING);

         }

    #endif

     

     

    Related Products

    This article applies to 5 products

    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Cyclone® V SX SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA