Article ID: 000077359 Content Type: Troubleshooting Last Reviewed: 10/19/2023

Why does the IP upgrade fail for Intel® Arria® 10 FPGA Native PHY Intel® FPGA IP with manual CTLE mode and DFE enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Transceiver Native PHY Intel® Arria® 10 Cyclone® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Intel® Arria® 10 FPGA Native PHY Intel FPGA IP, the IP upgrade to the Intel® Quartus® Prime Software version 16.0 from previous software versions might fail if you set CTLE mode to "manual" and enable DFE for data rates < 4.5 Gbps. The valid DFE mode is "disabled" when CTLE mode = "manual". You might also observe IP upgrade failure if the Native PHY Intel FPGA IP has multiple reconfiguration profiles enabled and if any profile has a configuration with CTLE mode = "manual" and DFE enabled for data rates < 4.5 Gbps

    Resolution

    To fix this problem, follow these steps:

    1. Open the Native PHY Intel FPGA IP in the IP parameter editor.
    2. Load the configuration profile with CTLE mode = "manual" and DFE enabled for data rates < 4.5 Gbps.
    3. Set DFE mode to "disabled".
    4. Save and generate your IP.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs