Article ID: 000077548 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why can't the Intel J3 flash devices configure the FPGA after power cycle when "Halt" upon failure option is selected for the MAX® II Parallel Flash Loader (PFL)?

Environment

  • MicroBlaster™ Fast Passive Parallel Software Driver
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This issue is only found in Intel J3 flash device family when the "Halt" upon failure option is selected in the PFL megafuntion.

    To fix this problem, add a delay circuitry to the nReset pin that pull this nReset pin low for a while before allowing it to go high. The minimum recommended delay time is 2ms.

    Another solution is to select "Retry Same page" or "Retry from Fixed address" at the action required for configuration failure option.

    Related Products

    This article applies to 1 products

    MAX® II CPLDs