Description
For Stratix II devices, the VCCIO for side I/O banks (1, 2, 5, 6) using LVDS inputs or outputs requires 2.5V.
Clock input pins on the top / bottom banks (3, 4, 7, 8) use VCCINT, so the VCCIO can be different to support other I/O standards on those banks (the Quartus® II default is 3.3V).
The PLL output pins on banks 9, 10, 11, and 12 require 3.3V VCCIO to drive LVDS signals.