Article ID: 000077587 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What VCCIO voltages are necessary for Stratix® II LVDS I/O standards for different banks?

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BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

For Stratix II devices, the VCCIO for side I/O banks (1, 2, 5, 6) using LVDS inputs or outputs requires 2.5V.

Clock input pins on the top / bottom banks (3, 4, 7, 8) use VCCINT, so the VCCIO can be different to support other I/O standards on those banks (the Quartus® II default is 3.3V).

The PLL output pins on banks 9, 10, 11, and 12 require 3.3V VCCIO to drive LVDS signals.

Related Products

This article applies to 1 products

Stratix® II FPGAs