Article ID: 000077611 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How do I disable the rx_data_align port in the ALTLVDS_RX megafunction?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem using the ALTLVDS_RX megafunction in the Quartus® II software version 10.0 and 10.0 SP1, you cannot remove the rx_data_align input port in the MegaWizard™ Plug-In Manager. Although you can enable and disable the option with the check box, the rx_data_align port remains as an input port to the megafunction.

If you do not want to use this port in your design, manually edit the VHDL or Verilog HDL variation file using the instructions below:

  • For VHDL:
    • In the PORT section of the ENTITY declaration, remove the line rx_data_align : IN STD_LOGIC_VECTOR (n DOWNTO 0)
    • In the PORT section of the COMPONENT declaration, remove the line rx_data_align : IN STD_LOGIC_VECTOR (n DOWNTO 0)
    • In the GENERIC MAP section of the ALTLVDS_RX_component instantiation, change the value of port_rx_data_align from "PORT_USED" to "PORT_UNUSED"
    • In the PORT MAP section of the ALTLVDS_RX_component instantiation, remove the line rx_data_align => rx_data_align
  • For Verilog HDL:
    • In the port list for the module declaration, remove the port rx_data_align
    • In the signal list for the module declaration, remove the line input [n:0] rx_data_align;
    • In the ALTLVDS_RX_component instantiation, remove the line
      .rx_data_align (rx_data_align)
    • In the defparam section for the ALTLVDS_RX_component instantiation, change the value of ALTLVDS_RX_component.port_rx_data_align from "USED" to "UNUSED"
  • n is the channel count -1

This problem is scheduled to be fixed in a future version of the Quartus II software.

Related Products

This article applies to 4 products

Cyclone® III FPGAs
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