Article ID: 000077894 Content Type: Troubleshooting Last Reviewed: 03/21/2022

Why don’t my F-Tile PMA/FEC Direct PHY Intel FPGA IP Debug Endpoint on Datapath Avalon Interface and Debug Endpoint on PMA Avalon Interface work in the Intel® Quartus® Prime Pro Edition Software versions 21.2 ?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, the F-Tile PMA/FEC Direct PHY Intel FPGA IP Debug Endpoint on Datapath Avalon Interface and Debug Endpoint on PMA Avalon Interface are not working.

    If you enable these two Avalon Interface options in the F-Tile PMA/FEC Direct PHY Intel FPGA IP, you will not be able to read/write and access to registers stored in the reconfiguration space of the FEC and the PMA interface block and the PMA.

    Resolution

    A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 21.2. Download and install Patch 0.16 from the appropriate link below.

    Download patch 0.16 for Windows (quartus-21.2-0.16-windows.exe)
    Download patch 0.16 for Linux (quartus-21.2-0.16-linux.run)
    Download the Readme for patch 0.16 (quartus-21.2-0.16-readme.txt)

    Alternatively, to work around this problem, you can instantiate external JTAG to Avalon Master Bridge Intel FPGA IP from the IP Catalog and connect the equivalent reconfiguration signals to the F-Tile PMA/FEC Direct PHY Intel FPGA IP Debug Endpoint on Datapath Avalon Interface and Debug Endpoint on PMA Avalon Interface signals.

    This method also allows you to read/write and access to the registers stored in the reconfiguration space of the FEC and the PMA interface block and the PMA.

    Additional information

    This problem is fixed starting with the Intel® Quartus® Prim Pro Edition Software version 21.4.

    Related Products

    This article applies to 2 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series
    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series