Article ID: 000078105 Content Type: Product Information & Documentation Last Reviewed: 08/27/2013

How can I connect clock pins and PLL output clocks to the Global Clock Control Block in Stratix® II devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When selecting the clock source dynamically, you can select between the sources in the following pairs:

  • Two PLL outputs (such as the C0 or C1 outputs from one PLL)
  • Two PLLs (such as the C0/C1 clock output of one PLL or the C0/C1 clock output of the other PLL)
  • Two clock pins (such as CLK0 or CLK1)
  • A combination of a clock pins and a PLL output

Clock pins can only connect to ports 0 and 1 of the clock control block. PLL outputs can only connect to ports 2 and 3 of the clock control block. Even numbered CLK and PLL output counters connect to even input ports of the ALTCLKCTRL block, odd numbered CLK and PLL output counters connect to odd ports of the ALTCLKCTRL block.

If the design only uses the two PLL output clocks on a clock control block without any clock pins, the MegaWizard® Plug-In Manager instantiation must still have 4 ports because PLL outputs can only connect to ports 2 and 3 of the clock control block.

Refer to the Clocking Section in the Stratix II handbook, Volume 2, Chapter 1 for an understanding of possible combinations to any one clock control block. For example, for Global Clock 0, its clock control block can accept inputs from clock pins CLK0p and CLK1p, and the C0 and C1 outputs from PLL1.