Article ID: 000078705 Content Type: Error Messages Last Reviewed: 10/15/2012

Critical Warning : Active Serial configuration mode is selected without INIT_DONE pin enabled. Depending on the configuration setup and board design, INIT_DONE pin may need to be enabled in the design.

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may get this Critical Warning message, when targetting a Stratix® V, Arria® V or Cyclone® V device and you have not enabled the optional INIT_DONE function in your Quartus® II project.

Resolution

In Active Serial (AS) multi-device configuration mode, Altera recommends that the INIT_DONE output pin option is enabled in the Quartus II software for devices in the configuration chain. Do not tie INIT_DONE pins together between master and slave devices. Monitor the INIT_DONE status for each device to ensure successful transition into user-mode.

Related Products

This article applies to 13 products

Stratix® V E FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V SE SoC FPGA
Cyclone® V E FPGA
Arria® V SX SoC FPGA
Arria® V ST SoC FPGA
Arria® V GZ FPGA
Arria® V GX FPGA
Arria® V GT FPGA