Article ID: 000079100 Content Type: Product Information & Documentation Last Reviewed: 01/31/2013

How do I infer the pre-adder in the Variable Precision DSP Block of a Cyclone V device?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

To infer the pre-adder in the Variable Precision DSP Block of the Arria® V, Cyclone® V, and Stratix® V device families be sure to resize your data inputs to the pre-adder by an additional bit to account for the carry within the pre-adder function. 

Resolution

To see an example of what this might look like use the Quartus II software templates available from the Edit > Insert Template... > VHDL > Full Designs > Arithmetic > DSP Features (Stratix-V, Arria-V and Cyclone-V).  Select one of the multiplier templates with operands from the pre-adder, for example Multiplier with One Operand from Pre-Adder template. 

These same templates are also available via the Verilog templates.

Related Products

This article applies to 9 products

Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V E FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Arria® V GT FPGA