Article ID: 000079147 Content Type: Troubleshooting Last Reviewed: 10/17/2011

During simulation of a XAUI core, the rx_errdetect signal might not be asserted when the rx_disperr signal is asserted for Stratix IV GX

Environment

Quartus Edition

Quartus® II Subscription Edition

Version Found: 9.1

FPGA Intellectual Property

Simulation

Version Found: 9.1

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

During simulation of a XAUI core, before data is valid, the rx_errdetect signal might not be asserted when the rx_disperr signal is asserted.

Resolution

If the rx_disperr signal is asserted before valid data is received, ignore the signal.

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