Due to a bug in the testbench, the monitor file altpcietb_pipe_xtx2yrx.v generates false errors during reset.
Since these checks are intended for external PIPE mode only, it should be disabled when the design runs in Serial mode.
Below are some of the error messages:
# ERROR: 196 ns TxElecIdle not asserted while reset asserted, Lane: 0, MAC: EP
# ERROR: 196 ns Powerdown not P1 while reset asserted, Lane: 0, MAC: EP
To suppress these errors, you must do the following:
1. Open <project_dir>/<variant>_examples/common/testbench/altpcietb_pipe_xtx2yrx.v and goto line 189
2. Qualify (pipe_mode == 1'b1) term to the original condition or replace it with the new code
The original RTL Verilog code:
if ((resetn == 1'b0) & (resetn_q1 == 1'b0) & (resetn_q2 == 1'b0) & (X_lane_conn == 1'b1))
The new RTL Verilog code:
if ((resetn == 1'b0) & (resetn_q1 == 1'b0) & (resetn_q2 == 1'b0) & (X_lane_conn == 1'b1) & (pipe_mode == 1'b1))
This problem will be fixed in a future version of Quartus® II software.