Article ID: 000079491 Content Type: Troubleshooting Last Reviewed: 10/29/2012

Why signal fixedclk_locked is not in the port list?

Environment

  • Quartus® II Subscription Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In the Stratix®  V Hard IP PCIe core v12.0, the fixedclk is driven by Serdes reference clock input ref_clk directly, so the signal fixedclk_locked signal is removed from the port list.

     

    Resolution

     

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA