Article ID: 000079780 Content Type: Troubleshooting Last Reviewed: 01/20/2012

Downstream Memory Reads (MRds) Fail for Arria V Hard IP for PCI Express

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Downstream memory reads (MRds) fail for all variants of the Arria V Hard IP for PCI Express IP core. No MRd TLP is generated on the Avalon Streaming (Avalon-ST) RX bus.

    Resolution

    The workaround is to drive the rx_st_mask signal with application logic or from an input pin instead of connecting it to ground. Connecting rx_st_mask to application logic or an input pin prevents the Quartus II software from removing rx_st_mask during optimization. For more information about the rx_st_mask signal, refer to the Arria V Hard IP for PCI Express User Guide.

    This issue is fixed in version 12.0 of the Quartus II software.

    Related Products

    This article applies to 1 products

    Arria® V FPGAs and SoC FPGAs