Article ID: 000080003 Content Type: Product Information & Documentation Last Reviewed: 05/25/2023

How do I connect the clock and reset for an Intel® Arria® 10 FPGA HPS hard memory controller when the FPGA is not programmed?

Environment

  • Quartus® II Subscription Edition
  • Clock
  • Reset
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    Description

    The Intel® Arria® 10 FPGA HPS hard memory controller (HMC) can be used while the FPGA fabric is unconfigured, but the phase-locked loop (PLL) reference clock and reset signals must be configured in a specific way.

    Resolution

    Only the I/O column must be configured initially for the HPS HMC to become useable; the FPGA fabric does not need to be configured.

    The PLL reference clock for the HPS HMC is recommended to come from the I/O bank’s dedicated input clock pins.  In the Platform Designer, you connect the HPS HMC’s Clock Input (pll_ref_clk_clock_sink) port to a Clock Source that is exported to connect to the dedicated input clock pins or export this signal directly.

    The global_reset_n input of the HPS HMC cannot be used if the FPGA fabric is unconfigured. Additionally, this global reset would reset the entire I/O column, not just the I/O banks used for the HPS HMC.  In the Platform Designer, you export the HPS HMC’s Reset Input (global_reset_reset_sink) signal or you may tie this to a Reset Source that can be used after the FPGA fabric is configured.

    The HPS can indirectly reset the HPS HMC via registers in the IOAUX calibration space accessible by the HPS. Two eight-bit busses (core2seq and seq2core) exist between the HPS and I/O column allowing software to write and read to registers in the Nios® II memory space.  The Reset Manager of the HPS handles the handshaking with the Nios® II processor through these busses (defined as ports hmc_gpio_core2seq and hmc_gpio_seq2core).  These GPIO ports are a hard connection between the HPS and the I/O column.  To request a reset and recalibration of the HPS HMC, software can write 0x0f to the core2seq register to kick-off the handshake.

    Handshake between HPS and Nios II processor

    Nios II processor polls the core2seq register until the software writes a 0x0f to the core2seq register.

    Nios II processor will write 0x07 on seq2core bus to acknowledge it has seen the reset request and has started the process.

    HPS will poll the seq2core until it sees that Nios II processor has written 0x08 indicating reset and recalibration is done.

    HPS will write 0x00 to core2seq to acknowledge that the Nios II processor has finished.


    Nios II processor will write 0x00 to seq2core to complete the handshake.

    In Summary

    You should reset the HPS first, then have the HPS reset the HMC indirectly through the Nios II processor.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 SX SoC FPGA