Article ID: 000080126 Content Type: Troubleshooting Last Reviewed: 08/21/2023

Why does my Stratix® V Hard IP for PCI Express in Gen3 configuration fail to link up to L0 after toggling pin PERST in simulation?

Environment

  • PCI Express
  • Simulation
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When simulating Stratix® V and Arria® V GZ Hard IP for PCI Express® as an Endpoint, the PCIe Hard IP can become stuck at Speed. Recovery if the Hard IP is reset after linking up to Gen3 L0. This is a known issue in the simulation model and has no impact on hardware.

    Resolution

    The issue will be fixed in a future Quartus® II software release.

    Related Products

    This article applies to 4 products

    Arria® V GZ FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Stratix® V GX FPGA

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