Article ID: 000080435 Content Type: Troubleshooting Last Reviewed: 10/13/2021

Why does the DMA write performance of the Intel® Stratix® 10 PCIe* Avalon®-MM Hard IP  implemented in Platform Designer degrade with Intel® Quartus® Prime Pro version 19.1?

Environment

  • Intel® Quartus® Prime Pro Edition
  • QSYS Example Designs
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-MM Intel® Stratix® 10 Hard IP+ for PCI Express
  • Avalon-MM Stratix® V Hard IP for PCI Express Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When using Intel® Quartus® Prime Pro version 19.1, the Intel® Stratix® 10 PCIe* Avalon®-MM Hard IP with DMA has a performance issue for DMA writes when using Platfrom Designer Avalon®-MM interconnect, which results in decreased throughput.

     

     

    Resolution

    Standalone implementations not using Platform Designer are not affected by this problem.

    If using Intel® Quartus® Prime Pro version 19.1, then download and install the patch 0.08 below to fix the DMA write efficiency problem.

     

    Download the Intel® Quartus® Prime Pro version 19.1 patch 0.08 for Windows (.exe)

    Download the Intel® Quartus® Prime Pro version 19.1 patch 0.08 for Linux (.run)

    Download the Readme for the Intel® Quartus® Prime Pro version 19.1 patch 0.08 (.txt)

     

    This problem is fixed starting with the Intel® Quartus® Prime Pro software version 19.2.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs