Description
Due to a problem in the Intel® Stratix® 10 Avalon® -ST Hard IP for PCIe* Design Example version 18.1 , you may observe this error when the "Generate HDL format" option is set to VHDL.
Resolution
To work around this problem in the Intel® Quartus® Prime Pro Edition software version 18.1 set the "Generate HDL format" option to Verilog. This problem has been fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.1