Article ID: 000082956 Content Type: Product Information & Documentation Last Reviewed: 10/19/2018

How do I access the Transceiver PHY register space using the phy_mgmt_addr port of the Serial Lite III Streaming Intel® FPGA IP Core for Intel® Stratix® 10 L-/H-Tiles?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Serial Lite III Streaming Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    To access the Transceiver PHY register space using the phy_mgmt_addr port of the Serial Lite III Streaming Intel® FPGA IP Core  for Intel® Stratix® 10 L-/H-Tiles, use the MSB of the bus as follows:

    •     Set phy_mgmt_addr[msb] = 1 to access the Intel Stratix 10 L-/H-Tile Transceiver PHY register space
    •     Set phy_mgmt_addr[msb] = 0 to access the  Serial Lite III Streaming Intel FPGA IP Core Configuration and Status Registers (CSR)
    Resolution

    This address usage will be documented in a future revision of the Serial Lite III Streaming Intel FPGA IP Core User Guide.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs