Article ID: 000085834 Content Type: Error Messages Last Reviewed: 03/23/2023

Critical Warning: *_p0_pin_map.tcl: Failed to find PLL clock for pins *:s0|*:sequencer_scc_mgr_inst|scc_state_curr.STATE_SCC_IDLE

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You will see this critical warning message if you compile DDR3 Controller with UniPHY with the following assignment. In this case, the Quartus® II software cannot find pll_config_clock.

set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES OFF

The Quartus II software will look for *:s0|*:sequencer_scc_mgr_inst|scc_state_curr.STATE_SCC_IDLE to search pll_config_clock.

The state will disappear if you disallow state machine generation. Thus, the Quartus® II software cannot find the clock.

Resolution

This problem has been fixed in Intel® Quartus® Prime Edition Software version 13.1.

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