You may get the following warning message when using the Quartus® II software:
Warning: The PLL is not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
This is a generic PLL warning for all Altera® devices. In Cyclone® III devices, "neighboring PLLs" do not exist because there is only a maximum of 4 PLLs at each corner of the device. As such, you can ignore the term neighboring PLL in the warning when targetting Cyclone III devices, however, Altera recommends driving the PLL through its dedicated clock input pin.