The SmartVID feature is implemented via a soft IP in the Intel® Arria® 10 FPGA core. As such, the FPGA logic needs to be configured successfully before SmartVID is functional. If you use the Early I/O Configuration method to boot the Intel® Arria® 10 HPS first prior to configuring the FPGA, the SmartVID feature will not be available until the FPGA core configuration is complete.
Ensure that both the VCC and VCCP of the device are powered with a fixed nominal voltage (0.90V) during Early I/O configuration. Once the FPGA configuration is complete, the SmartVID IP will be able to request the power regulator to update the value of VCC and VCCP.