Article ID: 000086981 Content Type: Troubleshooting Last Reviewed: 05/18/2013

Stratix V Avalon-MM Hard IP for PCI Express IP Core Signal Change when Multiple Packets Per Cycle Enabled

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In version 12.0 of the Quartus II software, if you enable Multiple packets per cycle in the Stratix V Hard IP for PCI Express IP Core GUI, the following top-level ports change from one-bit to two-bits: rx_st_valid, rx_st_err, tx_st_valid, and tx_st_err. Bit 1 of each two-bit vector applies to the upper two qwords of data. Bit 0 of each vector applies to the lower two qwords of data. The Stratix V Hard IP for PCI Express User Guide defines these ports as one bit.

    Resolution

    This issue is fixed in version 12.0 SP1 of the Quartus II software..

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs