Why does the Intel Agilex® 7 F-Tile SDI II FPGA IP design example fail to compile at the Support-Logic Generation stage?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.4, the Intel Agilex® 7 F-Tile SDI II FPGA IP design example will fail at the Support-Logic Generation stage during compilation with the following error message:

Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings.

A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 21.4. 

Download and install Patch 0.01 from the following links:

• Version 21.4 Patch 0.01 for Windows (.exe) 
• Version 21.4 Patch 0.01 for Linux (.run)
• Readme for version 21.4 Patch 0.01 (.txt)

This problem is being fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.1.