OpenCL™ Host Pipe Design Example

Recommended for:

  • Device: Unknown

  • Quartus®: v17.1

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This example introduces the use of Host Pipes. They are used for direct communication between the Kernel running on the FPGA and the Host code. The communication is done over the PCIe* bus, instead of going through DDR.

Features

  • Basic OpenCL API
  • Host Pipe API for map/unmap transfers
  • OpenCL events and event profiling

Downloads

The design example provides source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux* package includes a Makefile and the Windows package includes a Microsoft Visual Studio 2010 project.

The following downloads are provided for this example:

The use of this design is governed by, and subject to, the terms and conditions of the hardware reference design license agreement.

Software and Hardware Requirements

This design example requires the following tools:

  • Intel® FPGA software v17.1 or later
  • Intel FPGA SDK for OpenCL v17.1 or later
  • On Linux: GNU Make and gcc
  • On Windows: Microsoft Visual Studio 2010
  • Intel® Arria® 10 PCIe Gen3x8 with target device as a10gx_hostch

To download the Intel design tools, visit the OpenCL download page. The requirements for the underlying operating system are the same as those of the Intel FPGA SDK for OpenCL.

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.