Simulation Design Examples

Recommended For:

  • Device: Stratix® II

  • Device: Cyclone® II

  • Quartus®: v11.0 - v12.0

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Verification

Intel provides a suite of verification intellectual property (IP) cores, such as bus functional models (BFMs), to simulate the behavior of Avalon® Memory-Mapped (Avalon-MM) master and slave interfaces and Avalon® Streaming (Avalon-ST) source and sink interfaces. Verification components also include monitors to verify both Avalon protocols.

Designs targeted for the Intel® MAX® 10 device family and its development kits are available in the Design Store.

Simulation

Intel provides a suite of verification intellectual property (IP) cores, such as bus functional models (BFMs), to simulate the behavior of Avalon Memory-Mapped (Avalon-MM) master and slave interfaces and Avalon Streaming (Avalon-ST) source and sink interfaces. Verification components also include monitors to verify both Avalon protocols.