The Timing Analyzer makes it easy to use Synopsys® Design Constraint (SDC) commands to constrain complex clock structures, such as multiplexed clocks. The following shows three example circuits and the appropriate SDC commands to constrain them.
Assume that the clk port is driven by an off-chip multiplexer that selects between two clocks, one with a 10 ns period and one with an 8 ns period. The following SDC commands show how to assign multiple clocks to the clk port. It also shows how to add an exception indicating that the two clocks will never be active at the same time in the FPGA.
# Create the two clocks on the port create_clock -name clk_100 -period 10 [get_ports clk] create_clock -name clk_125 -period 8 [get_ports clk] -add # Set the two clocks as exclusive clocks set_clock_groups -exclusive -group {clk_100} -group {clk_125}
Assume that the clkA port is driven by a clock with a 10 ns period, and that the clkB port is driven by a clock with an 8 ns period. The following SDC commands show how to assign the clocks. This example is similar to the previous example, but the clocks are assigned to separate ports.
# Create a clock on each port create_clock -name clk_100 -period 10 [get_ports clkA] create_clock -name clk_125 -period 8 [get_ports clkB] -add # Set the two clocks as exclusive clocks set_clock_groups -exclusive -group {clk_100} -group {clk_125}
In this case, you must use the set_clock_groups command to indicate that clocks A and D, A and B, C and D, and B and C, can never be active at the same time.
create_clock -name A -period 10 [get_ports clkA] create_clock -name B -period 8 [get_ports clkB] create_clock -name C -period 8 [get_ports clkC] create_clock -name D -period 10 [get_ports clkD] # cut paths between clocks set_clock_groups -exclusive -group {A C} -group {B D}