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1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide
1.2. Design Example Detailed Description
1.3. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
1.4. Document Revision History for the JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
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1.2.1. Features
This design example has the following key features:
- System Console using Tcl script control mechanism
- Synthesis and simulation flows
- Configurable transport layer and pattern generator and checker modules
- Power-on self test with the following configurable test patterns:
- Alternating
- Ramp
- PRBS
- Supports simplex (RX only, TX only) and duplex (both RX and TX) data path modes
- Supports option for 3-wire SPI