AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

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ID 683387
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. List of Abbreviations 2. Introduction 3. Intel® Stratix® 10 FPGA Package Mechanical Design 4. Intel® Stratix® 10 FPGA Thermal Design Parameters 5. Thermal Design Process for Intel® Stratix® 10 Devices 6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices 7. Maximum Power and Typical Power 8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator
3. Intel® Stratix® 10 FPGA Package Mechanical Design x
3.1. Intel® Stratix® 10 Physical Package Structure
4. Intel® Stratix® 10 FPGA Thermal Design Parameters x
4.1. Intel® Stratix® 10 Compact Thermal Model (CTM) 4.2. Intel® Stratix® 10 Temperature Sensing 4.3. Thermal Sensor Accuracy
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices x
6.1. Device Selection 6.2. Logic Design Information 6.3. Thermal Settings and Parameters 6.4. Thermal Design Optimization 6.5. Updating Thermal Parameters 6.6. Intel® Stratix® 10 Device with PCIe Thermal Design Example 1 6.7. Heat Sink 6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method)
6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method) x
6.8.1. Analyzing 1U Sled with 3 FPGAs
1. List of Abbreviations
2. Introduction
3. Intel® Stratix® 10 FPGA Package Mechanical Design
4. Intel® Stratix® 10 FPGA Thermal Design Parameters
5. Thermal Design Process for Intel® Stratix® 10 Devices
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices
7. Maximum Power and Typical Power
8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

6.1. Device Selection

The first step in the design process is to select an FPGA device.

For the purpose of this example, we are using a 1SM21BE Intel® Stratix® 10 device, which has the following characteristics:

  • 1 core die
  • 1 H-Tile transceiver die
  • 3 E-Tile transceiver dies
  • 2 HBM dies
Table 3.   Intel® Stratix® 10 FPGA 1SM21BE Details
Feature Value Comment
Family Intel® Stratix® 10  
Device 1SM21BE Intel® Stratix® 10 FPGA with 7 die, core fabric, H-Tile, 3 E-Tiles, 2 HBM dies.
Package F55 55x55mm BGA package
Device Grade Extended -2-smart-VID  
Transceiver Grade EU1  
Figure 7. Top View of 1SM21BE Die Layout

The following figure shows the main page of the PTC updated with device information and all other fields at default values. The power summary at the left side predicts 6.447 watts of power dissipation. This is typical static power for this device when not instantiated, and with all dies at 25°C.

If we change the power characteristics to maximum or increase the junction temperature, the power consumption also increases. For more information on these relationships, refer to the Static Power and Typical Power topic, below.

Figure 8. PTC Main Page Updated with Device Information

Note in the message window in the above figure, Typical power calculations should not be used for regulator sizing and thermal analysis. This message occurs because the Power characteristics field is set to Typical, however the PTC activates it's thermal calculation only when the Power Characteristic field is set to maximum. To calculate all thermal parameters with maximum static power, set Power characteristics to maximum.

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