Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 4/01/2024
Public
Document Table of Contents

5.4. Managing Logic Design Files

The Quartus® Prime software helps you create and manage the logic design files in your project. Logic design files contain the logic that implements your design. When you add a logic design file to the project, the Compiler automatically includes that file in the next compilation. The Compiler synthesizes your logic design files to generate programming files for your target device.

The Quartus® Prime software includes full-featured schematic and text editors, as well as HDL templates to accelerate your design work. The Quartus® Prime software supports VHDL Design Files (.vhd), Verilog HDL Design Files (.v), and SystemVerilog (.sv). In addition, you can combine your logic design files with Intel and third-party IP core design files, including combining components into a Platform Designer system (.qsys).

CAUTION:
Starting from the Quartus® Prime Pro Edition software version 23.3, the compiler cannot synthesize schematic Block Design File (.bdf). For more information, refer to Converting Symbolic BDF Files to Acceptable File Formats.

The New Project Wizard prompts you to identify logic design files. Add or remove project files by clicking Project > Add/Remove Files in Project. View the project’s logic design files in the Project Navigator.

Figure 53. Design and IP Files in Project Navigator

Right-click files in the Project Navigator to:

  • Open and edit the file
  • Remove File from Project
  • Set as Top-Level Entity for the project revision
  • Create a Symbol File for Current File for display in schematic editors
  • Edit file Properties