AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel Stratix 10 Devices

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ID 683529
Date 5/24/2018
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Document Table of Contents
Document Table of Contents x
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization (ILA)
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices

1.1. Hardware Requirements

The hardware checkout test requires the following hardware and software tools:

  • Intel® Stratix® 10 GX H-Tile FPGA Development Kit (ES Edition)(1SG280HU1F50E1VGS1)
  • ADI AD9208 EVM
  • Micro-USB cable
  • MMPX-to-SMA cables
  • Clock source card capable of generating ADC sampling clock and FPGA device clock frequencies as listed in Table 6.
    Note: In this application note, the Analog Devices ADF4355 clock source card is used. Review the clocking scheme with the clock source card manufacturer of your choice.
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