AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

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ID 683803
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families x
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview x
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices x
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example x
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis x
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Design Example Guidelines for Intel® Arria® 10 Devices

These steps are applicable to Intel® Arria® 10 devices using Intel® Quartus® Prime Standard Edition only. Ensure that you use the GPIO Intel® FPGA IP core.
  1. Open the StratixV_blvds.qar file to import the Stratix® V design example into the Intel® Quartus® Prime Standard Edition software.
  2. Migrate the design example to use the GPIO Intel® FPGA IP core:
    1. On the menu, select Project > Upgrade IP Components.
    2. Double click the "ALIOBUF" entity.
      The MegaWizard Plug-In Manager window for the ALTIOBUF IP core appears.
    3. Turn off Match project/default.
    4. In Currently selected device family, select Arria 10.
    5. Click Finish and then click Finish again.
    6. In the dialog box that appears, click OK.
      The Intel® Quartus® Prime Pro Edition software performs the migration process and then displays the GPIO IP parameter editor.
  3. Configure the GPIO Intel® FPGA IP core to support a bidirectional input and output buffer:
    1. In Data Direction, select Bidir.
    2. In Data width, enter 1.
    3. Turn on Use differential buffer.
    4. Click Finish and generate the IP core.
  4. Connect the modules and the input and output ports as shown in the following figure:
    Figure 8. Input and Output Ports Connection Example for Intel® Arria® 10 Devices


  5. In the Assignment Editor, assign the relevant I/O standard as shown in the following figure. You can also set the current strength and slew rate options. Otherwise, the Intel® Quartus® Prime Standard Edition software assumes the default settings for Intel® Arria® 10 devices—Differential SSTL-18 Class I or Class II I/O standard.
    Figure 9. BLVDS I/O Assignment in the Intel® Quartus® Prime Assignment Editor for Intel® Arria® 10 Devices


    Note: For Intel® Arria® 10 devices, you can manually assign both the p and n pin locations for LVDS pins with the Assignment Editor.
  6. Compile and perform functional simulation with the ModelSim* - Intel® FPGA Edition software.
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