E-Tile Hard IP Intel Agilex® 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 8/08/2023
Public

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4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers

Table 49.   E-Tile Dynamic Reconfiguration Design Example Hardware Design Examples Register Map for 100G Ethernet ProtocolLists the memory mapped register ranges for all 100G Ethernet dynamic reconfiguration hardware design example variants. You access these registers with the reg_read and reg_write functions in the System Console.
Channel Number Word Offset Register Type
0 0x100000 Transceiver registers
0x000000 10G/25G Ethernet registers
0x010000 RS-FEC configuration registers
0x004000 100G Ethernet registers
0x005000 100G Packet Client and Packet Generator registers
0x001000 10G/25G Packet client and Packet Generator registers
1 0x300000 Transceiver registers
0x200000 10G/25G Ethernet registers
0x201000 10G/25G Packet Client and Packet Generator registers
2 0x500000 Transceiver registers
0x400000 10G/25G Ethernet registers
0x401000 10G/25G Packet Client and Packet Generator registers
3 0x700000 Transceiver registers
0x600000 10G/25G Ethernet registers
0x601000 10G/25G Packet Client and Packet Generator registers
Table 50.  100G Ethernet Dynamic Reconfiguration Registers For a specific address, use the 100G Ethernet registers word offset.

Addr

Name

Bit

Description

HW Reset Value

Access

0x00 dr_status [0] Reconfiguration controller status

Indicates the reconfiguration controller is busy. Don't modify the configuration while busy.

0x0 RW
0x09 dr_control [0] Reconfiguration process control

Set to 1 to trigger the reconfiguration process.

0x0 RW
0x0E dr_reset [3:0] Reset sequence

Reset all signals except the PMA and E-Tile Hard IP for Ethernet CSRs.

0x0 RW
0x13 cdr_cfg_ch_en [16,3:0] Channel enable
  • [16]: Enables lane 0 in 100G Ethernet variant
  • [3:0]: Enables lane 3 ~ lane 0 in 25G Ethernet variant
0x0 RW
0x14 dr_cfg_ch_ mode

[26:24,

18:16,

10:8,

2:0]

Channel mode

MAC+PCS: 0x5

  • [26:24]: Selects channel 3
  • [18:16]: Selects channel 2
  • [10:8]: Selects channel 1
  • [2:0]: Selects channel 0
0x0 RW
0x15 dr_cfg_fec_ pam4 [9] FEC PAM4
Protocol mode selection
  • [0]: NRZ
  • [1]: PAM4
Note: This register setting is introduced starting from Intel® Quartus® Prime Pro Edition software v22.3 .
0x15 RW
dr_cfg_fec_ mode [8] FEC Mode
FEC mode selection
  • [0]: KR-FEC(528,514)
  • [1]: KP-FEC(544,514)
Note: This register setting is introduced starting from Intel® Quartus® Prime Pro Edition software v22.3 for E-Tile.
0x15 RW
dr_cfg_fec_en [3:0] Enable RS-FEC on Nth channel 0x0 RW
0x16 dr_cfg_ch_ rate [3:0] Ethernet channel rate
  • [0]: Selects 25G/100G
0x0 RW