AN 876: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 F-Tile Devices

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ID 728670
Date 11/30/2023
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 F-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 F-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Summary 1.9. Document Revision History for AN 876: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 F-Tile Devices
1.4. Interoperability Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer (TL)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment (SHA) 1.4.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 F-Tile Devices

1.1. Hardware and Software Requirements

The interoperability test requires the following hardware and software tools:

Hardware

  • Intel Agilex® 7 I-Series F-Tile Demo Board (AGIB027R29A1E2VR0) with 12V power adapter
  • Analog Devices (ADI) AD9081 MxFE* EVM (AD9081-FMCA-EBZ, Rev C)
  • Skyworks Si5345-D* Evaluation Board (Si5345-D-EVB)
  • SMA male to SMP male
  • SMP male to SMP cable

Software

  • Intel® Quartus® Prime Pro Edition software version 21.4
  • AD9081_API version 1.1.0 or newer (Linux application, required for AD9081 EVM configuration)
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