Agilex™ 5 FPGAs and SoCs Device Overview

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ID 762191
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 5 FPGAs and SoCs 2. Agilex™ 5 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs 7. Core Clock Network in Agilex™ 5 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs 9. I/O PLLs in Agilex™ 5 FPGAs and SoCs 10. External Memory Interface in Agilex™ 5 FPGAs and SoCs 11. Hard Processor System in Agilex™ 5 SoCs 12. Transceivers in Agilex™ 5 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs 18. Device Security for Agilex™ 5 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs 20. Power Management for Agilex™ 5 FPGAs and SoCs 21. Software and Tools for Agilex™ 5 FPGAs and SoCs 22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 5 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 5 FPGAs and SoCs 1.2. Agilex™ 5 FPGAs and SoCs Block Diagram 1.3. Agilex™ 5 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 5 SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan x
2.1. Agilex™ 5 FPGAs and SoCs D-Series 2.2. Agilex™ 5 FPGAs and SoCs E-Series 2.3. Agilex™ 5 FPGAs and SoCs Package Options 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 5 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 5 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 5 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 5 FPGAs and SoCs
1. Overview of the Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs
7. Core Clock Network in Agilex™ 5 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs
9. I/O PLLs in Agilex™ 5 FPGAs and SoCs
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs
11. Hard Processor System in Agilex™ 5 SoCs
12. Transceivers in Agilex™ 5 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs
18. Device Security for Agilex™ 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs
20. Power Management for Agilex™ 5 FPGAs and SoCs
21. Software and Tools for Agilex™ 5 FPGAs and SoCs
22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview

14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs

Most of the Agilex™ 5 FPGAs and SoCs packages use the VPBGA package design. The E-Series FPGAs also offer 0.5 mm ball pitch package with a standard ball grid for small form-factor with more I/O counts.

Compared to the standard ball grid array (BGA) packages, the VPBGA package has a variable ball pitch size with a minimum size of 0.65 mm 22 .

Figure 14. Comparison Between Standard BGA and VPBGA


The variable ball pitch helps reduce the package form factor. Despite the smaller package size, the VPBGA packages can provide the same I/O pin count and compatible electrical performance compared to the standard BGA packages.

As shown in the following figure, the variable ball grid pattern eases trace routability, reducing the design complexity, number of PCB layers, and board thickness and size—ultimately, reducing board cost and development time.

Figure 15. Example of PCB Trace Routing for Variable Pitch BGA (VPBGA) Package


22 0.65 mm is the minimum ball pitch and is not meant for signal trace routing. The VPBGA design meets the 0.8 mm design rules and the use of standard plated through hole (PTH) via.
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