FIR II IP Intel® FPGA IP: User Guide

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ID 683208
Date 5/10/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the FIR II IP Intel® FPGA IP 2. FIR II IP Getting Started 3. FIR II IP Parameters 4. FIR II IP Functional Description 5. Document Revision History for the FIR II IP User Guide A. FIR II IP Core Document Archive
1. About the FIR II IP Intel® FPGA IP x
1.1. DSP Intel® FPGA IP Features 1.2. FIR II IP Core Features 1.3. FIR II IP Device Support 1.4. DSP Intel® FPGA IP Verification 1.5. FIR II IP Release Information 1.6. FIR II IP Core Performance and Resource Utilization
2. FIR II IP Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the FIR II IP Testbench in MATLAB 2.6. DSP Builder Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. FIR II IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
3. FIR II IP Parameters x
3.1. FIR II IP Core Filter Specification 3.2. FIR II IP Core Coefficient Settings 3.3. FIR II IP Core Coefficients 3.4. FIR II IP Core Input and Output Options 3.5. FIR II IP Core Implementation Options 3.6. FIR II IP Core Reconfigurability
3.3. FIR II IP Core Coefficients x
3.3.1. Loading Coefficients from a File
3.4. FIR II IP Core Input and Output Options x
3.4.1. Signed Fractional Binary 3.4.2. MSB and LSB Truncation, Saturation, and Rounding
3.5. FIR II IP Core Implementation Options x
3.5.1. Memory and Multiplier Trade-Offs
3.5.1. Memory and Multiplier Trade-Offs x
3.5.1.1. Using Memory Block Threshold 3.5.1.2. Using Dual-port RAM Threshold 3.5.1.3. Using Large RAM Threshold 3.5.1.4. Using Hard Multiplier Threshold
4. FIR II IP Functional Description x
4.1. FIR II IP Core Interpolation Filters 4.2. FIR Decimation Filters 4.3. FIR II IP Time-Division Multiplexing 4.4. FIR II IP Core Multichannel Operation 4.5. FIR II IP Multiple Coefficient Banks 4.6. FIR II IP Coefficient Reloading 4.7. Reconfigurable FIR Filters 4.8. FIR II IP Core Interfaces and Signals
4.4. FIR II IP Core Multichannel Operation x
4.4.1. Vectorized Inputs 4.4.2. Channelization 4.4.3. Channel Input and Output Format
4.4.3. Channel Input and Output Format x
4.4.3.1. Eight Channels on Three Wires 4.4.3.2. Four Channels on Four Wires 4.4.3.3. 15 Channels with 15 Valid Cycles and 17 Invalid Cycles 4.4.3.4. 22 Channels with 11 Valid Cycles and 9 Invalid Cycles 4.4.3.5. Super Sample Rate
4.8. FIR II IP Core Interfaces and Signals x
4.8.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.8.2. FIR II IP Core Avalon-ST Interfaces 4.8.3. FIR II IP Signals 4.8.4. FIR Filter Reset
4.8.2. FIR II IP Core Avalon-ST Interfaces x
4.8.2.1. Avalon-ST Sink Interface 4.8.2.2. Avalon-ST Source Interface
4.8.2.1. Avalon-ST Sink Interface x
4.8.2.1.1. Single Channel on Single Wire 4.8.2.1.2. Multiple Channels on Single Wire 4.8.2.1.3. Multiple Channels on Multiple Wires
1. About the FIR II IP Intel® FPGA IP
2. FIR II IP Getting Started
3. FIR II IP Parameters
4. FIR II IP Functional Description
5. Document Revision History for the FIR II IP User Guide
A. FIR II IP Core Document Archive

5. Document Revision History for the FIR II IP User Guide

Date Quartus Prime Version IP Version Changes
2024.05.10 24.1 19.2.4 Updated Timing Diagram of Coefficient Reloading in Read Mode
2024.04.15 24.1 19.2.4
  • Added FIR Filter Reset
  • Added new parameters: Internal Delay-Lines Rezeroed on Warm-Reset, Simulation Tests Warm-Reset, Coefficient Sharing, Reset Minimization.
2024.04.01 24.1 19.2.4
  • Added support for Agilex™ 5 devices
2023.06.26 23.2 -
  • Added support for Agilex™ 7 devices
  • Added coeff_out_waitrequest signal
2020.06.02 17.1 Changed Input Sample Rate value in the Filter Specification Parameter table
2017.11.06 17.1 Added support for Cyclone® 10 devices
2016.05.01 16.0
  • Renamed memory and multiplier tradeoff parameters
  • Added resource estimation to implementation parameters
  • Renamed Coefficients parameters table to Coefficient settings.
  • Created new parameter tables: Coefficients and Reconfigurability.
  • Added simulating testbench in MATLAB.
  • Added interpolation and decimation filter descriptions.
2015.10.01 15.1
  • Added interpolation factor to defintion of i
  • Added reconfigurable FIR filters
  • Added signal descriptions:
    • coeff_in_clk
    • coeff_in_areset
    • coeff_in_read
2014.12.15 14.1
  • Added full support for Arria 10 and MAX 10 devices
  • Reordered parameters tables to match wizard
  • Updated loading coefficients from a file instructions.
August 2014 14.0 Arria 10 Edition
  • Added support for Arria 10 devices.
  • Added Arria 10 generated files description.
  • Removed table with generated file descriptions.
June 2014 14.0
  • Corrected TDM timing diagram TDM_output_data signal.
  • Removed device support for Cyclone III and Stratix III devices
  • Added support for MAX 10 FPGAs.
  • Added instructions for using IP Catalog
November 2013 13.1
  • Corrected coefficient file description.
  • Removed device support for following devices:
    • HardCopy II, HardCopy III, HardCopy IV E, HardCopy IV GX
    • Stratix, Stratix GX, Stratix II, Stratix II GX
    • Cyclone, Cyclone II
    • Arria GX
May 2013 13.0 Updated interpolation and decimation factor ranges.
November 2012 12.1 Added support for Arria V GZ devices.
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